Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/129895
Title: Removing Data Dependencies in the CCSDS 123.0-B-2 Predictor Weight Updating
Authors: Barrios Alfaro,Yubal 
Bartrina-Rapestà, Joan
Hernández-Cabronero, Miguel
Sánchez Clemente, Antonio José 
Blanes, Ian
Serra-Sagrista, Joan
Sarmiento Rodríguez, Roberto 
UNESCO Clasification: 33 Ciencias tecnológicas
Keywords: hyperspectral imaging
onboard data processing
Compression algorithms
Issue Date: 2024
Project: Lossless/lossy multispectral & hyperspectral compression IP core 
Journal: IEEE Geoscience and Remote Sensing Letters 
Abstract: The Consultative Committee for Space Data Systems (CCSDS) first standardized near-lossless coding capabilities in the CCSDS 123.0-B-2 algorithm. However, this standard does not describe strategies to produce high-throughput hardware implementations, which are not trivial to derive from its definition. At the same time, throughput optimizations without significant compression performance penalty are paramount to enable real-time compression on-board next-generation satellites. This work demonstrates that the weight update stage of the CCSDS 123.0-B-2 predictor can be selectively bypassed to enhance throughput for both lossless and near-lossless modes with minimal impact on compression performance and still produce fully compliant bitstreams. Skipping the weight update implies that those weights must be carefully chosen outside the original CCSDS 123.0-B-2 pipeline. Two strategies are proposed to select effective weight values based on whether a priori information about the current image is exploited or not. Comprehensive experimental results are presented for both proposed strategies and for lossless and near-lossless regimes, using a representative set of hyperspectral images. The coding penalty is, on average, 1% for lossless and 8% for near-lossless, depending on the strategy used to set the initial weights. The proposed method obtains a maximum throughput of one processed sample per clock cycle when it is evaluated using high-level synthesis (HLS), consuming 4.6% of the look-up tables (LUTs) and 31.1% of the internal memory on a Xilinx Kintex UltraScale space-grade field programmable gate array (FPGA).
URI: http://hdl.handle.net/10553/129895
ISSN: 1558-0571
DOI: 10.1109/LGRS.2024.3362376
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